RD RAM

System Cost: Memory Granularity

          An RDRAM system has a very compelling memory advantage over competing SDRAM or DDR-based systems. Since a single RDRAM device can act as an entire memory subsystem, the granularity of the memory footprint is a single device: 32 MB for today’s 256 Mb densities of RDRAM and 64 MB for tomorrow’s 512 M bit generation. 64-bit DDR systems on the other hand, have a minimum granularity of 128 MB using x16 devices in 256 M bit technology. The granularity problem is illustrated in the table. Applications such as networking, communications and consumer electronics can take advantage of RDRAM memory’s single device performance to optimize the total memory footprint while providing the highest system performance.

Packaging- An Overview

Rambus systems can be classified either as short Channel systems or as long Channel systems depending on the electrical length of the Rambus Channel. Long Channel systems typically have eight or more RDRAMs per Channel and consist of a motherboard and one or more memory modules. Such an arrangement allows the user to expand the memory size either by increasing the number of modules plugged into the motherboard or by using higher capacity modules. The impedance of long Channel systems is generally constrained to 28_ because of the need to conform to the impedance of available memory modules. Short Channel systems typically have fewer than five RDRAMs per Channel and are implemented on a common motherboard. An example of a short Channel system is a graphics controller which uses RDRAMs for the frame buffer.

Introduction

             In this quest for speed, most of the attention is focused on the microprocessor. But a PC’s memory is equally important in supporting the new capabilities of visual computing. And commodity Dynamic RAMs (DRAMs), the mainstay of PC memory architecture, have fallen behind the microprocessor in their ability to handle data in the volume necessary to support complex graphics. While device densities have increased by nearly six orders of magnitude, DRAM access times have only improved by 10. Over the same time, microprocessor performance has jumped by a factor of 100. In other words, while bus frequency has evolved from 33 MHz for EDO to the current standard of 100 Mhz for SDRAMs and up to 133 MHz for the latest PC-133 specification, memory speed has been out spaced by the operation frequency of the microprocessor which reached 600 MHz plus by the turn of the century. Thus, the memory subsystem risked to become a bottleneck for overall system performance or had created a significant performance gap between computing elements and their associated memory devices.

The High-Speed Memory Interface

          The Direct Rambus™ ASIC Cell (Direct RAC) is a library macrocell used in ASIC designs to interface the core logic of a CMOS ASIC device to a high-speed Direct Rambus Channel. The Direct RAC incorporates all of the high-speed interface circuitry and logic necessary to provide the ASIC designer full access and control over the Direct Rambus Channel without forcing any particular design implementation. The Direct RAC is flexible enough to be used for implementations ranging from simple memory controllers, complex multi-port memory controllers, or as a communication path for high speed chip-to-chip interface.

Performance

          Memory performance is usually summarized by two measures: bandwidth and latency. Peak system bandwidth can be defined as the maximum transfer rate of a particular memory technology given ideal conditions. Effects particular to each memory system degrade this peak bandwidth to a lower number called effective bandwidth. Effective bandwidth can be expressed as the product of peak bandwidth and efficiency, a measure of the ability of the memory system to deliver on its peak bandwidth given real world memory transaction patterns. In addition to examining the pitfalls of bandwidth measures, it is also important to look at latency. Devices are usually characterized by component latency, which is the time between row strobe and the delivery of the first bit of data on the output pin for an individual component.

 Abstract

               During the last two decades, there has been an exponential growth in the  operational speed of microprocessors. Also RAM capacities have been improving at more than fifty percent per year. However the speed and access time of the memory have been improving at slower rate. In order to keep up in performance and reliability with processor technology it is necessary to make considerable improvements in the memory access time.

Conclusion

          RDRAM memory ensures that the computing experience is unbounded by memory and increases the lifecycle of systems.