BiCMOS Technology

BiCMOS

BiCMOS technologies possess better integration capability than bipolar-only technologies. It is not possible to develop very-high-density digital circuits in bipolar-only technologies, as these bipolar logic circuits consume static power. Also of importance to SOC systems is the vast set of large macro cells, including microprocessors, memory macros, and DSPs, that are available in most CMOS technologies, as well as the computer-aided design (CAD) infrastructure for multi-million gate systems, that exist in fine-line CMOS technologies.

About

          The history of semiconductor devices starts in 1930’s when Lienfed and Heil first proposed the mosfet. However it took 30 years before this idea was applied to functioning devices to be used in practical applications, and up to the late 1980 this trend took a turn when MOS technology caught up and there was a cross over between bipolar and MOS share.CMOS was finding more wide spread use due to its low power dissipation, high packing density and simple design, such that by 1990 CMOS covered more than 90% of total MOS scale.

System On Chip (Soc) Fundamentals

The concept of system-on-chip (SOC) has evolved as the number of gates available to a designer has increased and as CMOS technology has migrated from a minimum feature size of several microns to close to 0.1 µm. Over the last decade, the integration of analog circuit blocks is an increasingly common feature of SOC development, motivated by the desire to shrink the number of chips and passives on a PC board. This, in turn, reduces system size and cost and improves reliability by requiring fewer components to be mounted on a PC board. Power dissipation of the system also improves with the elimination of the chip input-output (I/O) interconnect blocks. Superior matching and control of integrated components also allows for new circuit architectures to be used that cannot be attempted in multi-chip architectures. Driving PC board traces consume significant power, both in overcoming the larger capacitances on the PC board and through larger signal swings to overcome signal cross talk and noise on the PC board.

Process Integration Of The Sige Device

Next consider the low-cost integration of SiGe bipolar devices with the core CMOS process for mixed RF, analog, and digital SOC chips. Figure 1 shows a cross section of the silicon wafer with both the CMOS and SiGe bipolar devices. The addition of a SiGe bipolar transistor module introduces a low-cost, high-performance, super-self-aligned (double-poly) graded SiGe base NPN transistor to the CMOS process. In a double polysilicon bipolar transistor, the base and emitter polysilicon define the placements of the base and emitter regions, respectively. The emitter is formed using arsenic-doped poly. The capacitances from emitter to base (Ceb) and from base to collector (Cbs) are reduced because no extra implant width is required to account for registration errors between the active element of the device and its contact.

Capacitors

          Without any modules, a CMOS process offers only the gate-semiconductor capacitance for capacitor formation. Not only is this highly nonlinear as the device transition from accumulation to depletion, but it also results in a parasitic junction capacitance on silicon side of the device that makes the capacitor incompatible for many circuits. Traditional CMOS processes designed for analog-and mixed-signal applications have included an extra layer of polysilicon to form a poly-poly capacitor. This capacitor is much more linear and its parasitic capacitance from the lower poly layer to the substrate is significantly reduced.

Abstract

          The need for high-performance, low-power, and low-cost systems for network transport and wireless communications is driving silicon technology toward higher speed, higher integration, and more functionality. Further more, this integration of RF and analog mixed-signal circuits into high-performance digital signal-processing (DSP) systems must be done with minimum cost overhead to be commercially viable. While some analog and RF designs have been attempted in mainstream digital-only complimentary metal-oxide semiconductor (CMOS) technologies, almost all designs that require stringent RF performance use bipolar or semiconductor technology.

Inductors

          Conflicting substrate requirements limit the integration of high-Q inductors with high-performance CMOS devices. Inductors fabricated using CMOS technologies based on epi/p+ substrates [Figure 8a) are severely degraded because of eddy-current losses in the substrate, and typically maximum quality-factor Q reported on epi/p+ substrates is only 3.

 Conclusion

Presented an overview of a SiGe modular BiCMOS process technology. Through the use of add-on modules compatible with the core CMOS process technology, large-scale chips combining digital, analog, and RF technologies can be produced. Modules are added as required by the chip under development. By using the core process with added modules, the economies of scale associated with large-volume CMOS production are maintained without compromising the performance of the analog or RF circuits.