Chip Morphing

About

Engineering is a study of tradeoffs. In computer engineering the tradeoff has traditionally been between performance, measured in instructions per second, and price. Because of fabrication technology, price is closely related to chip size and transistor count. With the emergence of embedded systems, a new tradeoff has become the focus of design. This new tradeoff is between performance and power or energy consumption.

Processors for these devices must be able to deliver high performance with low energy dissipation. Additionally, these devices evidence large fluctuations in their performance requirements. Often a device will have very low performance demands for the bulk of its operation, but will experience periodic or asynchronous “spikes” when high-performance is needed to meet a deadline or handle some interrupt event.

Morph

These objectives and motivations were identified during the MORPH project, a part of the Power Aware Computing / Communication (PACC) initiative. In addition to exploring several mechanisms to fundamentally improve performance, the MORPH project brought forth the idea of “gear shifting” as an analogy for run-time reconfiguration. Realizing that real world applications vary their performance requirements dramatically over time, a major goal of the project was to design microarchitectures which could adjust to provide the minimal required performance at the lowest energy cost.

Caches

A similar sequence of techniques actually starts with designs for caches that are inherently low-power, and reduces total power without compromising the processor cycle time. This cache technique uses multiple line buffers with each data/tag array to hold the data and tag fields for a few recently-accessed cache sets (instead of the single line buffer encountered in conventional caches). Each such set of line buffers also has an associated “set number” latch that holds the set number corresponding to the current contents of that line buffer set.

Physical Memory

In the Morph project, however, the assumption that we can dynamically change the IPC of the CPU opens up additional opportunities for energy saving in these other components. Generally one designs a system to meet the peak performance of the CPU, in this case provide enough memory bandwidth at appropriate access latencies to feed the CPU fully. However, if the CPU can change its IPC, this means that its load on the rest of the system also changes, and what was designed for peak performance needs now becomes a potentially energy draining overkill.

Power Relationships

A superscalar machine is one where there are multiple function units to which multiple instructions can be issued in a single cycle. IW, the issue width, can be defined as the maximum number of instructions which can be so issued at a constant rate. Because of inter-instruction dependencies, long latency operations, speculative execution, and branches, the sustainable performance of such a CPU, denoted as IPC, is much lower than IW. To a first approximation we will assume a variant of Amdahl’s law here, namely that IPC grows as something like the square root of the IW.

Adding Gears

Given the above analysis, an interesting microarchitecture would be one where the IPC can be varied over a relatively large R, and where the EPC varies as above. The beginnings of such a design can be found in a class of microarchitectures termed “multi-cluster.”

Conversion Into A Gear

The idea behind converting a multi-cluster design into a morphable one is as follows. We start with, for example, a 4-cluster design where all 4 clusters are used at times of highest performance needs. As performance needs decrease, some of these clusters are deactivated, and the instructions that would have been issued to them are now issued to the other clusters. The result is clearly a lower effective IPC. However, we have lowered the energy used in the clusters approximately linearly, and can also lower the energy consumed in the fetch and decode sections by down-shifting the number of cycles in which it is active.

Abstract

 This seminar discusses results from the project called morph where the goal was to develop a micro architecture that can adapt it intrinsic performance  dynamically. By observing the power dissipation, reducing the performance characteristics thus reduces the power even faster, resulting in greatly improved performance/ watt characteristics .

Conclusion

This paper has attempted to introduce the main concepts in the Morph project, an attempt to approach low power embedded system in a novel way - by attacking power consumption during those frequent times when less than peak performance is needed.